Shreechetan Pudur

Shreechetan Pudur

@Shreex07

B.Tech ECE student | Exploring Core Electronics | Learning Digital & Analog Electronics | C programming | SystemVerilog Enthusiast

Bengaluru
2
Followers
5
Following
3
Public Repos
0
Private Repos

Language Breakdown

Lines of code distribution across 3 owned repositories

7K Total LOC
SystemVerilog
6,939 lines
100.0%
N/A
I

I-Shaped Developer

I-shaped

Specialist — deep expertise in SystemVerilog

SystemVerilog

Collaboration Network

Global Impact visualization

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Shreechetan Pudur
0 active collaborators

Repos

3

PRs

0

Growth

+18%

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Coding Streak

Contribution activity over the past year

3 days
19
Contributions
15
Commits
0
Pull Requests
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Followers 2
vishu-udedh

Vishvesh U V

@vishu-udedh

 brown178munde

ritesh naik

@brown178munde
Following
5 total
sasukeuchiha14

Hardik Garg

@sasukeuchiha14

 yani1505

Yashaswini

@yani1505

 vishu-udedh

Vishvesh U V

@vishu-udedh

 Pranav2005Desai

Pranav Vineet Desai

@Pranav2005Desai

 brown178munde

ritesh naik

@brown178munde
Synced via GitHub

Top Repositories

NegEdge_SR_FF_IC7400

Implementation of Negative Edge Triggered SR flip flop using IC7400

1 0
system-verilog

A collection of SystemVerilog codes for digital logic circuits, created as part of my learning.

1 0
SystemVerilog
Shreex07
0 0

Open Source Impact

Contributions to external projects

0 merged PRs

No external contributions found.